1. Field of the Invention
The present invention relates to power management apparatuses for achieving energy saving in, image forming apparatuses and the like, for example, and to image forming apparatuses and the like using the same.
2. Description of the Related Art
Energy saving is gaining more and more interest worldwide these days. There are a large number of laws and regulations related to energy saving, and recently, ErP Directive Lot 6/Lot 26 and the like have been specified. The requirements of the Lot 6 directive include provision of a mode of reducing electricity to 0.5 W or less. In other words, in order that an apparatus satisfies these directives, a power-saving mode is needed in which the power consumption reliably becomes a predefined electric power (0.5 W) or smaller. Also, the requirements of the Lot 26 directive include provision of a mode of reducing average consumed power to 2 Wh/h or smaller. In other words, it is necessary to promptly enter the power-saving mode so as to reduce average power consumption. In order to meet these regulations, it is effective to reduce electricity in an LSI (large-scale integrated circuit), which is one of the elements that consume a large amount of electricity among all elements constituting an apparatus. Examples of power-saving techniques for LSIs include the clock-gating technique and the power supply separation technique. The clock-gating technique defined here is a technique of stopping a clock signal supplied to modules within an LSI by software control. The power supply separation technique is a technique of separating power supplies for the respective module groups within an LSI, and shutting a module or modules off in units of module groups. Power that is consumed in an LSI can be roughly divided into leakage power that is consumed just by supplying the power to the LSI, and dynamic power that is consumed due to switching of a transistor at the time of clock supply and data processing. The clock-gating technique can reduce dynamic power, and it is a characteristic thereof that internal register values can be retained because this technique stops only clock supply. The power supply separation technique energy saving effect is higher than the clock-gating technique because it can reduce both leakage power and dynamic power, but is disadvantageous in that restart takes time because the internal register values are lost as a result of power supply shutoff. As a measure against long recovery time in an apparatus using the power supply separation technique, it has been proposed to introduce multiple modes of power control (a shutoff mode, voltage drop mode, hold mode, etc.) and select a power control mode in accordance with waiting time for a program to be executed next (e.g., see Japanese Patent Laid-Open No. 2003-345671, etc.). Also, it is characteristics of the value of leakage power that the value is low at low temperature and is high at high temperature. Focusing on such temperature characteristics of the leakage power, a method has been proposed of measuring the temperature inside an apparatus and controlling clock frequency and the power supply of functional blocks for varying them stepwise, in accordance with the measured temperature (e.g., see Japanese Patent Laid-Open No. 11-243604, etc.).
In Japanese Patent Laid-Open No. 2003-345671, the problem of long recovery time deriving from power shutoff is addressed by not interrupting power depending on waiting time for a program to be executed next. With this method, performance can be improved by not interrupting power in some cases, but in exchange therefore, electric power is consumed during this period of time because of not interrupting power, and effective energy saving cannot be achieved. In Japanese Patent Laid-Open No. 11-243604, the clock is slowed down and functional blocks are shut down if the temperature is high, in order to prevent runaway operations due to increased temperature. With this method, power consumption can be reduced to some extent. In Japanese Patent Laid-Open No. 11-243604, however, there is no mention of provision of the power-saving mode for meeting the requirement of reduction of power consumption to a predefined amount or smaller as specified in the aforementioned Lot 6 directive.
In other words, in order to reliably execute the power-saving mode in which the power consumption is reduced to 0.5 W or smaller as specified in the Lot 6 directive, it is necessary to reduce the power using the power supply separation technique with a high power-saving effect. However, the register values are lost and the context is also lost as a result of power supply shutoff, and therefore, long recovery time is necessary. With only the clock-gating technique, which is a power-saving method with which the recovery time is short, leakage power increases at high temperature because power is supplied uninterruptedly, and there is a possibility that an apparatus cannot reliably enter the power-saving mode in which power consumption is reduced to 0.5 W or smaller.